2.8. The program status registers

The ARM7EJ-S processor contains one CPSR, and five SPSRs for exception handlers to use. The program status registers:

The arrangement of bits in the status registers is shown in Figure 2.6, and described in:

Figure 2.6. Program status register

Note

The unused bits of the status registers might be used in future ARM architectures, and must not be modified by software. The unused bits of the status registers are readable, to enable the processor state to be preserved (for example, during process context switches) and writable, to enable the processor state to be restored. To maintain compatibility with future ARM processors, and as good practice, you are strongly advised to use a read-modify-write strategy when changing the CPSR.

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