2.9.1. Exception entry and exit summary

Table 2.3 shows the PC value preserved in the relevant r14 on exception entry, and the recommended instruction for exiting the exception handler.

Table 2.3. Exception entry and exit

Exception or entry

Return instruction

Previous state

Notes

ARM r14_x

Thumb r14_x

Jazelle r14_x

SWI

MOVS PC, R14_svc

PC + 4

PC+2

-

Where the PC is the address of the SWI or undefined instruction. Not used in Jazelle state.

UNDEF

MOVS PC, R14_und

PC + 4

PC+2

-

PABT

SUBS PC, R14_abt, #4

PC + 4

PC+4

PC+4

Where the PC is the address of the instruction that had the Prefetch Abort.

FIQ

SUBS PC, R14_fiq, #4

PC + 4

PC+4

PC+4

Where the PC is the address of the instruction that was not executed because the FIQ or IRQ took priority.

IRQ

SUBS PC, R14_irq, #4

PC + 4

PC+4

PC+4

DABT

SUBS PC, R14_abt, #8

PC + 8

PC+8

PC+8

Where the PC is the address of the Load or Store instruction that generated the Data Abort.

RESET

NA

-

-

-

The value saved in r14_svc upon reset is UNPREDICTABLE.

BKPT

SUBS PC, R14_abt, #4

PC + 4

PC+4

PC+4

Software breakpoint.

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