2.9.3. Leaving an ARM exception

When an exception has completed, the exception handler must move the LR, minus an offset to the PC. The offset varies according to the type of exception, as shown in Table 2.3.

If the S bit is set and rd is r15, the core copies the SPSR back to the CPSR and clears the interrupt disable flags that were set on entry.


The action of restoring the CPSR from the SPSR automatically resets the T bit and J bit to the values held immediately prior to the exception. The I and F bits are automatically restored to the value they held immediately prior to the exception.

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