A.1. Clock interface signals

Clock interface signals are shown in Table A.1.

Table A.1. Clock interface signals

Name

Direction

Description

CLK

Input

System clock. This clock times all operations in the ARM7EJ-S processor. All outputs change from the rising edge and all inputs are sampled on the rising edge. The clock can be stretched in either the LOW or HIGH phase. Synchronous wait states can be added using the CLKEN signal. Through the use of the DBGTCKEN signal, this clock also times debug operations.

CLKEN

Input

Wait-state control. The ARM7EJ-S processor can be stalled for integer clock cycles by driving CLKEN LOW. This signal must be held HIGH at all other times.

CORECLKENOUT

Output

The principal state advance signal for the ARM7EJ-S processor.

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