A.2. Memory interface signals

Memory interface signals are shown in Table A.2.

Table A.2. Memory interface signals

Name

Direction

Description

ABORT

Input

The memory abort or bus error is issued by the memory system to signal to the processor that a requested access is disallowed.

ADDR[31:0]

Output

The processor address bus.

LOCK

Output

Locked transaction operation:

  • when HIGH, the processor is performing a locked memory access

  • when LOW, the arbiter can enable another device to access the memory.

PROT[1:0]

Output

These indicate whether the output is opcode or data and whether access is in User or Privileged mode.

RDATA[31:0]

Input

The read data input bus is used to transfer instructions and data between the processor and memory. The data on this bus is sampled by the processor at the end of the clock cycle during read accesses.

SIZE[1:0]

Output

Memory access width indicates to the external memory system when a word, halfword, or byte length transfer is required:

  • b00 indicates a byte transfer

  • b01 indicates a halfword transfer

  • b10 indicates a word transfer

  • b11 is reserved.

TRANS[1:0]

Output

The next transaction type outputs indicate the type of the next transaction (internal, coprocessor, sequential, or non-sequential):

  • b00 indicates an internal cycle

  • b01 indicates a coprocessor register transfer cycle

  • b10 indicates a nonsequential cycle

  • b11 indicates a sequential cycle.

WDATA[31:0]

Output

The write data output bus is used to transfer data from the processor to the memory or coprocessor system. Write data is set up to the end of the cycle of write accesses and remains valid throughout wait states.

WRITE

Output

Write/read access:

  • when HIGH indicates a processor write cycle

  • when LOW, indicates a processor read cycle.

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