A.4. Miscellaneous signals

Miscellaneous signals are shown in Table A.4.

Table A.4. Miscellaneous signals

Name

Direction

Description

CFGBIGEND

Input

When HIGH, the ARM7EJ-S processor treats bytes in memory as being in big-endian format. When it is LOW, memory is treated as little-endian. This is a static configuration signal.

CFGDISLTBIT

Input

When HIGH, the ARM7EJ-S processor disables certain ARMv5TEJ defined behavior involving loading data to the PC. This input must be tied LOW for normal operation and full ARMv5TEJ compatibility. This is a static configuration signal.

CFGHIVECS

Input

When LOW, the ARM7EJ-S processor exception vectors start at address 0x0000 0000. When HIGH the ARM7EJ-S processor exception vectors start at address 0xFFFF 0000. This is a static configuration signal.

nRESET

Input

Not reset is used to start the processor from a known address. This is a level-sensitive asynchronous reset.

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