A.5. Coprocessor interface signals

Coprocessor interface signals are shown in Table A.5.

Table A.5. Coprocessor interface signals

Name

Direction

Description

CHSD[1:0]

Input

Coprocessor handshake decode. The handshake signals from the Decode stage of the pipeline follower of the coprocessor.

CHSE[1:0]

Input

Coprocessor handshake execute. The handshake signals from the Execute stage of the pipeline follower of the coprocessor.

CPCLKEN

Output

The coprocessor clock enable is the synchronous enable for the coprocessor pipeline follower. When HIGH on the rising edge of CLK, the pipeline follower logic is able to advance.

CPDIN[31:0]

Input

This is the 32-bit coprocessor write data bus for transferring data from the coprocessor.

CPDOUT[31:0]

Output

This is the 32-bit coprocessor read data bus for transferring data to the coprocessor.

CPEN

Input

Coprocessor enable. If no coprocessor is used in an embedded ARM7EJ-S processor design, this signal must be tied to LOW to save power. This is a static signal.

CPINSTR[31:0]

Output

This is the 32-bit coprocessor instruction bus over which instructions are transferred to the coprocessor pipeline follower.

CPJBIT

Output

The coprocessor instruction Jazelle bit. When HIGH, this indicates that the ARM7EJ-S processor is in Jazelle state. This signal is sampled by the coprocessor pipeline follower.

CPLATECANCEL

Output

If the coprocessor late cancel signal is HIGH during the first memory cycle of a coprocessor instruction, then the coprocessor must cancel the instruction without changing any internal state. This signal is only asserted in cycles where theprevious instruction accessed memory and a Data Abort occurred.

CPnMREQ

Output

This is the coprocessor not memory request. When the signal is LOW on the rising edge of CLK and CPCLKEN is HIGH, the instruction of CPINSTR must enter the coprocessor pipeline.

CPnTRANS

Output

The not memory translate signal:

  • when LOW, indicates that the processor is in User mode

  • when HIGH, indicates that the processor is in Privileged mode.

This signal is sampled by the coprocessor pipeline follower.

CPPASS

Output

This signal indicates that there is a coprocessor instruction in the Execute stage of the pipeline that must be executed.

CPTBIT

Output

Coprocessor instruction Thumb bit. When HIGH, indicates that the ARM7EJ-S processor is in Thumb state. This signal is sampled by the coprocessor pipeline follower.

Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B
Non-Confidential