A.6. Debug signals

The debug signals are shown in Table A.6.

Table A.6. Debug signals

Name

Direction

Description

DBGACK

Output

Debug acknowledge. When HIGH, indicates that the processor is in debug state.

DBGCOMMRX

Output

Debug Communications Channel (DCC) receive. When HIGH, this signal denotes that the DCC receive buffer contains valid data waiting to be read by the processor.

DBGCOMMTX

Output

DCC transmit. When HIGH, this signal denotes that the DCC transmit buffer is empty.

DBGEBKPT

Input

Debug breakpoint. This signal is asserted by the external hardware to halt execution of the processor for debug purposes. It will cause the processor to enterdebug state if it is HIGH at the end of an instruction fetch, and that instruction reaches the Execute stage of the processor pipeline, or if it is HIGH at the end of a data memory request cycle.

DBGEN

Input

Debug enable. This signal allows the debug features of the processor to be disabled, it must be tied LOW when debugging is not required.

DBGEXT[1:0]

Input

EmbeddedICE external input. This input to the EmbeddedICE logic enables breakpoints and watchpoints to be dependent on external conditions.

DBGIR[3:0]

Output

TAP controller instruction register These four bits reflect the current instruction loaded into the TAP controller instruction register. These bits change when the TAP state machine is in the UPDATE-IR state.

DBGnTDOEN

Output

Not DBGTDO enable. When LOW, this signal denotes that serial data is being driven out on the DBGTDO output. DBGnTDOEN is usually used as an output enable for a DBGTDO pin in a packaged part.

DBGnTRST

Input

Not test reset. This is the active LOW reset signal for the EmbeddedICE internal state. This signal is a level-sensitive asynchronous reset input.

DBGRNG[1:0]

Output

EmbeddedICE Rangeout. This output indicates that the corresponding EmbeddedICE watchpoint unit has matched the conditions currently present on the address, data, and control buses. This signal is independent of the state of the enable control bit of the watchpoint unit.

DBGRQI

Output

Internal debug request. This signal represents the state of bit 1 of the debug control register that is combined with EDBGRQ and presented to the core debug logic.

DBGSCREG[4:0]

Output

Scan chain select number. These five bits reflect currently selected scan chain by the TAP Scan Chain Register controller. These bits change when the TAP state machine is in the UPDATE-DR state.

DBGSDIN

Output

Output boundary scan serial input data. This signal contains the serial data to be applied to an external scan chain.

DBGSDOUT

Input

Input boundary scan serial output data. This is the serial data out of an external scan chain. When an external boundary scan chain is not connected, this input must be tied LOW.

DBGTAPSM[3:0]

Output

TAP controller state machine This bus reflects the current state of the TAP controller state machine.

DBGTCKEN

Input

Synchronous enable for debug logic accessed using the JTAG interface.

DBGTDI

Input

Test data input to the debug logic.

DBGTDO

Output

Test data output from the debug logic.

DBGTMS

Input

Test mode select for the TAP controller.

EDBGRQ

Input

External debug request. An external debugger can force the processor to enter debug state by asserting this signal.

TAPID[31:0]

Input

Boundary scan ID code. This input specifies the ID code value shifted out on DBGTDO when the IDCODE instruction is entered into the TAP controller.

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