B.1. Scan chains and JTAG interface

There are two JTAG-style scan chains within the ARM7EJ-S processor. These enable debugging and EmbeddedICE-RT programming.

The scan chains enable commands to be serially shifted into the ARM core, enabling the state of the core and the system to be interrogated. The JTAG interface requires only five pins on the package.

A JTAG style Test Access Port (TAP) controller controls the scan chains. For further details of the JTAG specification, refer to IEEE Standard 1149.1 - 1990 Standard Test Access Port and Boundary-Scan Architecture.

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