B.6. Determining the core and system state

When the ARM7EJ-S processor is in debug state, you can examine the core and system state by forcing the load and store multiples into the instruction pipeline.

Before examining the core and system state, the debugger must determine whether the processor entered debug from Thumb state, ARM state or Jazelle state by examining bits 4 and 5 of the EmbeddedICE-RT debug status register. When bit 4 is set, the core has entered debug from Thumb state. When bit 5 is set, the core has entered debug from Jazelle state.When bit 4 and 5 is clear the core has entered debug from ARM state.

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