6.8. Debug Communications Channel

The EmbeddedICE-RT logic contains a Debug Communications Channel (DCC) for passing information between the target and the host debugger. This is implemented as coprocessor 14.

The DCC comprises:

These registers are located in fixed locations in the EmbeddedICE-RT logic register map (as described in EmbeddedICE-RT logic) and are accessed from the processor using MCR and MRC instructions to coprocessor 14.

In addition to the communications channel registers, the processor can access a bit 0 of the 32-bit debug status register for use in the monitor mode debug configuration.

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