6.2.3. The ARM7EJ-S processor

The ARM7EJ-S processor has hardware extensions that ease debugging at the lowest level. The debug extensions:

The major blocks of the ARM7EJ-S processor are:

ARM7EJ-S core

This is the processor core, with hardware support for debug.

EmbeddedICE-RT logic

This is a set of registers and comparators used to generate debug exceptions (such as breakpoints). This unit is described in About EmbeddedICE-RT.

TAP controller

This controls the action of the scan chains using a JTAG serial interface.

ETM interface

This interface facilitates connection of an Embedded Trace Macrocell (ETM) to the core. The ETM is described in the ETM9 (Rev 2a) Technical Reference Manual.

These blocks are shown in Figure 6.2.

Figure 6.2. Debug block diagram

In halt mode, a request on one of the external debug interface signals, or on an internal functional unit known as the EmbeddedICE-RT logic, forces the processor into debug state. The events that activate debug are:

The internal state of the processor is examined using the JTAG serial interface, that enables instructions to be serially inserted into the core pipeline without using the external data bus. So, for example, when in debug state, a store multiple (STM) instruction can be inserted into the instruction pipeline, and this exports the contents of the core registers. This data can be serially shifted out without affecting the rest of the system.

Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B
Non-Confidential