6.8.3. DCC monitor mode debug status register

The coprocessor 14 monitor mode debug status register is provided for use by a debug monitor when the processor is configured into the monitor mode debug mode.

The coprocessor 14 monitor mode debug status register is a 32-bit wide register with one read/write bit with the format shown in Figure 6.7.

Figure 6.7. Monitor mode debug status register

Bit 0 of the register, the DbgAbt bit, indicates whether the processor took a Prefetch or Data Abort in the past because of a breakpoint or watchpoint. If the core takes a Prefetch Abort as a result of a breakpoint or watchpoint, then the bit is set. If on a particular instruction or data fetch, both the debug abort and external abort signals are asserted, the external abort takes priority and the DbgAbt bit is not set. You can read or write the DbgAbt bit using MRC or MCR instructions.

A typical use of this bit is by a monitor mode debug aware abort handler. This examines the DbgAbt bit to determine whether the abort was externally or internally generated. If the DbgAbt bit is set, the abort handler initiates communication with the debugger over the communications channel.

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