6.9. Monitor mode debug

The ARM7EJ-S processor contains logic that enables the debugging of a system without stopping the core entirely. This enables the continued servicing of critical interrupt routines while the core is being interrogated by the debugger. Setting bit 4 of the DCC control register enables the monitor mode debug features of the core. When this bit is set, the EmbeddedICE-RT logic is configured so that a breakpoint or watchpoint causes the core to enter abort mode, taking the Prefetch or Data Abort vectors respectively.

There are several restrictions you must be aware of when the processor is configured for monitor mode debugging:

The fact that an abort has been generated by monitor mode is recorded in the monitor mode debug status register in CP14 (see DCC monitor mode debug status register).

Because the monitor mode debug bit does not put the core into debug state, it now becomes necessary to change the contents of the watchpoint registers while external memory accesses are taking place, rather than changing them when in debug state. If the watchpoint registers are altered during an access, all matches from the affected watchpoint unit using the register being updated are disabled for the cycle of the update.

If there is a possibility of false matches occurring during changes to the watchpoint registers, caused by old data in some registers and new data in others, then you must:

  1. Disable the watchpoint unit using the control register for that watchpoint unit.

  2. Alter the values in the other registers.

  3. Re-enable the watchpoint unit by rewriting the control register.

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