6.8.2. DCC control register

The DCC control register is read-only.

Note

The control register should be viewed as read-only. However, the debugger can clear the R bit by performing a write to the DCC control register. This feature must not be used under normal circumstances.

The register controls synchronized handshaking between the processor and the debugger. The DCC control register is shown in Figure 6.6.

Figure 6.6. DCC control register

The function of each register bit is described below:

Bits 31:28

Contain a fixed pattern that denotes the EmbeddedICE version number (b0110 in this case).

Bits 27:2

Are reserved.

Bit 1

Denotes if the communications data write register is available (from the viewpoint of the processor). Seen from the processor, if the communications data write register is free (bit 1 is clear), new data can be written. If the register is not free (bit 1 is set), the processor must poll until bit 1 is clear.Seen from the debugger, when W=1, some new data has been written that can then be scanned out.

Bit 0

Denotes if there is new data in the communications data read register. Seen from the processor, if bit 0 is clear, there is some new data that can be read using an MRC instruction.

Seen from the debugger, if bit 0 is set, the communications data read register is free, and new data may be placed there through the scan chain. If R=1, this denotes that data previously placed there through the scan chain has not been collected by the processor, and so the debugger must wait.

You can use the following instructions to access these registers:

MRC p14, 0, Rd, c0, c0

The above instruction returns the DCC control register into Rd.

MCR p14, 0, Rn, c1, c0

The above instruction writes the value in Rn to the communications data write register.

MRC p14, 0, Rd, c1, c0

The above instruction returns the debug data read register into Rd.

Note

The Thumb instruction set does not support coprocessor instructions. Therefore, the processor must be in ARM state before you can access the DCC.

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