6.3. About EmbeddedICE-RT

The EmbeddedICE-RT logic provides integrated on-chip debug support for the ARM7EJ-S processor.

EmbeddedICE-RT is programmed serially using the TAP controller. Figure 6.3 shows the relationship between the core, EmbeddedICE-RT, and the TAP controller. It only shows the signals that are pertinent to EmbeddedICE-RT.

Figure 6.3. Major debug components

The EmbeddedICE-RT logic comprises:

The debug control register and the debug status register provide overall control of EmbeddedICE-RT operation.

You can program one or both watchpoint units to halt the execution of instructions by the core. Execution halts when the values programmed into EmbeddedICE-RT match the values currently appearing on the address bus, data bus, and various control signals.

Note

You can mask any bit so that its value does not affect the comparison.

You can configure each watchpoint unit to be either a watchpoint (monitoring data accesses) or a breakpoint (monitoring instruction fetches). Watchpoints and breakpoints can be data-dependent in halt mode when in debug state.

The EmbeddedICE-RT logic can be configured into a mode of operation where watchpoints or breakpoints generate Data or Prefetch Aborts respectively. This enables a real-time debug monitor system to debug the processor while still allowing critical fast interrupt requests to be serviced.

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