10.10. AC timing parameter definitions

Table 10.9 shows target AC parameters. All figures are expressed as percentages of the CLK period at maximum operating frequency.

Note

Where 0% is given, this indicates the hold time to clock edge plus the maximum clock skew for internal clock buffering.

Table 10.9. Target AC timing parameters

Symbol

Parameter

Min

Max

Cross reference

Tihabort

ABORT input hold from rising CLK

15%

-

Figure 10.1

Tihcfg

Configuration input hold from rising CLK

15%

-Figure 10.3

Tihchsd

CHSD input hold from rising CLK

15%

-Figure 10.2

Tihchse

CHSE input hold from rising CLK

15%

-Figure 10.2

Tihclken

CLKEN input hold from rising CLK

15%

-

Figure 10.1

Tihcpdin

CPDIN input hold from rising CLK

15%-Figure 10.2

Tihdbgebkpt

DBGEBKPT input hold from rising CLK

15%

-Figure 10.4

Tihdbgin

Debug inputs input hold from rising CLK

15%

-Figure 10.4

Tihetmpwrdown

ETMPWRDOWN input hold from rising CLK

15%-Figure 10.8

Tihint

Interrupt input hold from rising CLK

15%

-Figure 10.3

Tihnreset

nRESET input hold from rising CLK

15%

-Figure 10.3

Tihntrst

DBGnTRST input hold from rising CLK

15%

-Figure 10.6

Tihrdata

RDATA input hold from rising CLK

15%

-

Figure 10.1

Tihtapid

TAPID input hold time from rising CLK

15%

-Figure 10.6

Tihtcken

DBGTCKEN input hold from rising CLK

15%

-Figure 10.6

Tihtdi

DBGTDI input hold from rising CLK

15%

-Figure 10.6

Tihtms

DBGTMS input hold from rising CLK

15%

-Figure 10.6

Tihtpid

TRACEPROCID[31:0] input hold from rising CLK

15%-Figure 10.8

Tihtpidwr

TRACEPROCIDWR input hold from rising CLK

15%-Figure 10.8

Tisabort

ABORT input setup to rising CLK

25%

-

Figure 10.1

Tiscfg

Configuration input setup to rising CLK

30%

-

Figure 10.3

Tischsd

CHSD input setup to rising CLK

35%

-

Figure 10.2

Tischse

CHSE input setup to rising CLK

35%

-

Figure 10.2

Tisclken

CLKEN input setup to rising CLK

40%

-

Figure 10.1

Tiscpdin

CPDIN input setup to rising CLK

35%-Figure 10.2

Tisdbgebkpt

DBGEBKPT input setup to rising CLK

25%

-Figure 10.4

Tisdbgin

Debug inputs input setup to rising CLK

25%

-

Figure 10.4

Tisetmpwrdown

ETMPWRDOWN input setup to rising CLK

25%-Figure 10.8

Tisint

Interrupt input setup to rising CLK

30%

-

Figure 10.3

Tisnreset

nRESET input setup to rising CLK

35%

-

Figure 10.3

Tisntrst

DBGnTRST input setup to rising CLK

25%

-

Figure 10.6

Tisrdata

RDATA input setup to rising CLK

25%

-

Figure 10.1

Tistapid

TAPID input setup to rising CLK

25%

-

Figure 10.6

Tistcken

DBGTCKEN input setup to rising CLK

35%

-

Figure 10.6

Tistdi

DBGTDI input setup to rising CLK

35%

-

Figure 10.6

Tistms

DBGTMS input setup to rising CLK

35%

-

Figure 10.6

Tistpid

TRACEPROCID[31:0] input setup time to rising CLK

25%-Figure 10.8

Tistpidwr

TRACEPROCIDWR input setup time to rising CLK

25%-Figure 10.8

Tohaddr

ADDR hold time from rising CLK

0%

-

Figure 10.1

Tohcpcontrol

CPnMREQ, CPnTRANS, CPTBIT, and CPJBIT hold from rising CLK0%-Figure 10.2

Tohcpdout

CPDOUT hold time from rising CLK

0%-Figure 10.2

Tohcpinstr

CPINSTR hold time from rising CLK

0%-Figure 10.2

Tohctl

Control hold time from rising CLK

0%

-

Figure 10.1

Tohdbgack

DBGACK hold time from rising CLK

0%

-

Figure 10.4

Tohdbgcomm

Communications channel output hold time from rising CLK

0%

-

Figure 10.4

Tohdbgrng

DBGRNG hold time from rising CLK

0%

-

Figure 10.4

Tohdbgrqi

DBGRQI hold time from rising CLK

0%

-

Figure 10.4

Tohdbgsm

Debug state hold from rising CLK

0%

-

Figure 10.6
Tohetm

ETM interface output signals hold from rising CLK

0%

-

Figure 10.8
TohintdisSensitive to interrupt status hold from rising CLK0%-Figure 10.5

Tohlate

CPLATECANCEL hold from rising CLK

0%

-

Figure 10.2

Tohpass

CPPASS hold time from rising CLK

0%

-

Figure 10.2

Tohsdin

DBGSDIN hold from rising CLK

0%

-

Figure 10.6

Tohtdo

DBGTDO hold from rising CLK

0%

-

Figure 10.6

Tohtdoen

DBGnTDOEN hold from rising CLK

0%

-

Figure 10.6

Tohtrans

Transaction type hold time from rising CLK

0%

-

Figure 10.1

Tohwdata

WDATA hold time from rising CLK

0%

-

Figure 10.1

Tovaddr

Rising CLK to ADDR valid

-

65%

Figure 10.1

Tovcpcontrol

Rising CLK to CPnMREQ, CPnTRANS, CPTBIT, and CPJBIT valid

-35%Figure 10.2

Tovcpdout

Rising CLK to CPDOUT valid

-35%Figure 10.2

Tovcpinstr

Rising CLK to CPINSTR valid

-35%Figure 10.2

Tovctl

Rising CLK to control valid

-

65%

Figure 10.1

Tovdbgack

Rising CLK to DBGACK valid

-

60%

Figure 10.4

Tovdbgcomm

Rising CLK to communications channel outputs valid

-

60%

Figure 10.4

Tovdbgrng

Rising CLK to DBGRNG valid

-

80%

Figure 10.4

Tovdbgrqi

Rising CLK to DBGRQI valid

-

45%

Figure 10.4

Tovdbgsm

Rising CLK to debug state valid

-

50%

Figure 10.6

Tovetm

Rising CLK to ETM interface output signals valid

-

20%

Figure 10.8
TovintdisRising CLK to Sensitive to interrupt status valid-70%Figure 10.5

Tovlate

Rising CLK to CPLATECANCEL valid

-

35%

Figure 10.2

Tovpass

Rising CLK to CPPASS valid

-

35%

Figure 10.2

Tovsdin

Rising CLK to DBGSDIN valid

-

50%

Figure 10.6

Tovtdo

Rising CLK to DBGTDO valid

-

50%

Figure 10.6

Tovtdoen

Rising CLK to DBGnTDOEN valid

-

60%

Figure 10.6

Tovtrans

Rising CLK to transaction type valid

-

65%

Figure 10.1

Tovwdata

Rising CLK to WDATA valid

-

60%

Figure 10.1

Ttdsd

DBGTDO delay from DBGSDOUT changing

-

-

Figure 10.7

Ttdsh

DBGTDO hold time from DBGSDOUT changing

-

-

Figure 10.7
Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B
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