B.1.2. TAP state machine

The process of serial test and debug is best explained in conjunction with the JTAG state machine. Figure B.2 shows the state transitions that occur in the TAP controller. The state numbers shown in the diagram are output from the ARM7EJ-S processor on the DBGTAPSM[3:0] signals.

Figure B.2. Test access port controller state transitions

From IEEE Std 1149.1-1990. Copyright 2001 IEEE. All rights reserved.

Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B
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