B.5.1. Bypass register

The Bypass register purpose, bit length, and operating mode description is given below:


Bypasses the device during scan testing by providing a path between DBGTDI and DBGTDO.


1 bit.

Operating mode

When the BYPASS instruction, or any undefined instruction, is the current instruction in the instruction register, serial data is transferred from DBGTDI to DBGTDO in the SHIFT-DR state with a delay of one CLK cycle enabled by DBGTCKEN.

A logic 0 is loaded from the parallel input of the bypass register in the CAPTURE-DR state. There is no parallel output from the bypass register.

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