B.5.3. Instruction register

The Instruction register purpose, bit length, and operating mode description is given below:


Specifies a TAP instruction.


4 bits.

Operating mode

In the SHIFT-IR state, the instruction register is selected as the serial path between DBGTDI and DBGTDO.

During the CAPTURE-IR state, b0001 is loaded into this register. This value is shifted out during SHIFT-IR (least significant bit first), while a new instruction is shifted in (least significant bit first).

During the UPDATE-IR state, the value in the instruction register specifies the current instruction.

On reset, IDCODE specifies the current instruction.

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