B.6.2. Determining the system state

To meet the dynamic timing requirements of the memory system, any attempt to access system state must occur synchronously. Therefore, the ARM7EJ-S processor must be forced to synchronize back to system speed. Bit 32 of scan chain 1, SYSSPEED, controls this.

You can place a legal debug instruction onto the instruction data bus of scan chain 1 with bit 32 (the SYSSPEED bit) clear. This instruction is then normally executed at debug speed. To execute an instruction at system speed, a NOP (such as MOV R0, R0) must be scanned in as the next instruction with bit 32 set.

After the system speed instructions are scanned into the instruction data bus and clocked into the pipeline, the RESTART instruction must be loaded into the TAP controller. This causes the ARM7EJ-S processor automatically to resynchronize back to CLK conditioned with CLKEN when the TAP controller enters RUN-TEST/IDLE state, and executes the instruction at system speed. Debug state is reentered once the instruction completes execution, when the processor switches itself back to CLK conditioned with DBGTCKEN. When the instruction completes, DBGACK is HIGH. At this point INTEST can be selected in the TAP controller, and debugging can resume.

To determine if a system speed instruction has completed, the debugger must look at SYSCOMP (bit 3 of the debug status register). The ARM7EJ-S processor must access memory through the data bus interface, as this access can be stalled indefinitely by CLKEN. Therefore, the only way to determine if the memory access has completed is to examine the SYSCOMP bit. When this bit is set, the instruction has completed.

The state of the system memory can be fed back to the debug host by using system speed load multiple instructions and debug speed store multiple instructions.

Instructions that can have the SYSSPEED bit set

There are restrictions on which instructions can have the SYSSPEED bit set. The valid instructions on which to set this bit are:

  • loads

  • stores

  • load multiple

  • store multiple.

When the ARM7EJ-S processor returns to debug state after a system speed access, the SYSSPEED bit is clear. The state of this bit gives the debugger information about why the core entered debug state the first time this scan chain is read.

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