B.7.4. Watchpoint with another exception

If a watchpointed access also has a Data Abort returned, the ARM7EJ-S processor enters debug state in Abort mode. Entry into debug is prevented until the core changes into Abort mode, and has fetched the instruction from the abort vector.

A similar sequence follows when an interrupt, or any other exception, occurs during a watchpointed memory access. The ARM7EJ-S processor enters debug state in the mode of the exception. The debugger must check to see if an exception has occurred by examining the current and previous mode (in the CPSR and SPSR), and the value of the PC. When an exception has taken place, you must be given the choice of servicing the exception before debugging.

For example, suppose that an abort has occurred on a watchpointed access and ten instructions have been executed in debug state. You can use the following sequence to return to program execution:

0 EAFFFFF1; Branch minus 15 addresses (two’s complement)

1 E1A00000; NOP (MOV R0, R0), SYSSPEED bit is set

This code forces a branch back to the abort vector, causing the instruction at that location to be refetched and executed.


After the abort service routine, the instruction that caused the abort and watchpoint is refetched and executed. This triggers the watchpoint again, and the ARM7EJ-S processor re-enters debug state.

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