B.9.1. Register map

The EmbeddedICE-RT logic register map is shown in Table B.4.

Table B.4. EmbeddedICE-RT logic register map

Address

Width

Function

Type

b00000

6

Debug control

Read/write

b00001

5

Debug status

Read-only

b00010

8

Vector catch control

Read/write

b00100

6

DCC control

Read-only[1]

b00101

32

DCC data

Read/write

b01000

32

Watchpoint 0 address value

Read/write

b01001

32

Watchpoint 0 address mask

Read/write

b01010

32

Watchpoint 0 data value

Read/write

b01011

32

Watchpoint 0 data mask

Read/write

b01100

9

Watchpoint 0 control value

Read/write

b01101

8

Watchpoint 0 control mask

Read/write

b10000

32

Watchpoint 1 address value

Read/write

b10001

32

Watchpoint 1 address mask

Read/write

b10010

32

Watchpoint 1 data value

Read/write

b10011

32

Watchpoint 1 data mask

Read/write

b10100

9

Watchpoint 1 control value

Read/write

b10101

8

Watchpoint 1 control mask

Read/write

[1] An attempted write to the DCC control register can be used to reset bit 0 of that register.

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