B.9.4. Watchpoint control registers

The control value and control mask registers are mapped identically in the lower eight bits shown in Figure B.7.

Figure B.7. Watchpoint control value and mask register format

Bit 8 of the control value register is the ENABLE bit and cannot be masked.

The bits have the following functions:


Compares against the write signal from the core to detect the direction of bus activity. Bit 0 is clear for a read cycle and set for a write cycle.


Compares against the SIZE[1:0] signal from the core to detect the size of bus activity.

The encoding is shown in Table B.5.

Table B.5. SIZE bits

Register bit 2

Register bit 1

Data size














Is used to detect whether the current cycle is an instruction fetch (bit 3 is clear), or a data access (bit 3 is set).


Is used to compare against the not translate signal from the core to distinguish between User mode accesses when bit 4 is clear, and non-User mode accesses when bit 4 is set.


Is an external input to EmbeddedICE logic that enables the watchpoint to be dependent on some external condition. The DBGEXT input for Watchpoint 0 is labeled DBGEXT[0]. The DBGEXT input for Watchpoint 1 is labeled DBGEXT[1].


Can be connected to the chain output of another watchpoint to implement, for example, debugger requests of the form:breakpoint on address YYY only when in process XXX.

In the EmbeddedICE-RT logic, the CHAINOUT output of Watchpoint 1 is connected to the CHAIN input of Watchpoint 0.

The CHAINOUT output is derived from a register. The address/control field comparator drives the write enable for the register. The input to the register is the value of the data field comparator.

The CHAINOUT register is cleared when the control value register is written, or when nTRST is LOW.


In the ARM7EJ-S EmbeddedICE-RT logic, the RANGEOUT output of Watchpoint 1 is connected to the RANGE input of Watchpoint 0. Connection enables the two watchpoints to be coupled for detecting conditions that occur simultaneously, such as for range checking.


When a watchpoint match occurs, the internal DBGBREAK signal is asserted only when the ENABLE bit is set. This bit exists only in the value register. It cannot be masked.

For each of the bits [7:0] in the control value register, there is a corresponding bit in the control mask register. These bits remove the dependency on particular signals.

Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B