B.9.6. Debug status register

The debug status register is ten bits wide. If it is accessed for a read (with the read/write bit LOW), the status bits are read. The format of the debug status register is shown in Figure B.9.

Figure B.9. Debug status register

The function of each bit in this register is shown in Table B.8.

Table B.8. Debug status register bit functions

Bit number

Name

Function

1:0

DBGRQ,

DBGACK

Enable the values on the synchronized versions of EDBGRQ and DBGACK to be read.

2

IFEN

Enables the state of the core interrupt enable signal to be read.

3

SYSCOMP

Enables the state of the SYSCOMP bit from the core to be read. This enables the debugger to determine that a memory access from the debug state has completed.

4

CPTBIT

Enables the status of the output CPTBIT to be read. This enables the debugger to determine what state the processor is in, and therefore which instructions to execute.

5

CPJBIT

Enables the status of the output CPJBIT to be read. This enables the debugger to determine what state the processor is in, and therefore which instructions to execute.

6:9

MOEThis provides Method of Entry (MOE) information to the debugger. On entry into debug state, the MOE field is updated to indicate the cause of debug entry. The MOE field can be read from the TAP side by accessing the EICE Debug Status Register. Table B.9 shows bit values and the associated meanings.

The structure of the debug control and status registers is shown in Figure B.10.

Table B.9. Method of entry

MOE[3:0]Meaning
b0000No debug entry (since last restart/dbg rst)
b0001Breakpoint from EICE unit 0
b0010Breakpoint from EICE unit 1
b0011Soft breakpoint (BKPT instruction)
b0100Vector catch breakpoint
b0101External breakpoint
b0110Watchpoint from EICE unit 0
b0111Watchpoint from EICE unit 1
b1000External watchpoint
b1001Internal debug request
b1010External debug request
b1011Debug re-entry from system speed access

Figure B.10. Debug control and status register structure

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