1.1.1. The instruction pipelines

The ARM7EJ-S processor uses a pipeline to increase the speed of the flow of instructions to the processor. This enables several operations to take place simultaneously, and the processing and memory systems to operate continuously.

A five-stage ARM state pipeline is used, consisting of Fetch, Decode, Execute, Memory, and Writeback stages. This is shown in Figure 1.1.

A six-stage pipeline is used in Jazelle state, consisting of Fetch, Jazelle, Decode, Execute, Memory, and Writeback stages. This is shown in Figure 1.2.

Figure 1.1. Five-stage pipeline

During normal operation:

Note

The program counter points to the instruction being fetched rather than to the instruction being executed.

Figure 1.2. Six-stage Jazelle pipeline

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