1.1.3. Forwarding, interlocking, and data dependencies

Due to the nature of the five-stage pipeline, a value can be required for use before it has been placed in the register bank by the actions of an earlier instruction. The ARM7EJ-S processor control logic automatically detects these cases and stalls the core or forwards data as applicable to overcome these hazards. No intervention is required by software in these cases, although you can improve software performance by re-ordering instructions in certain situations.

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