2.7.1. The ARM state register set

In ARM state, 16 general registers and one or two status registers are accessible at any one time. In privileged modes, mode-specific banked registers become available. Figure 2.3 shows which registers are available in each mode.

The ARM state register set contains 16 directly-accessible registers, r0 to r15. A further register, the Current Program Status Register (CPSR), contains condition code flags and the current mode bits. Registers r0 to r13 are general-purpose registers used to hold either data or address values. Registers r14, r15, and the CPSR have the following special functions:

Link register

Register r14 is used as the subroutine Link Register (LR).

Register r14 receives a copy of r15 when a Branch with Link (BL or BLX) instruction is executed.

You can treat r14 as a general-purpose register at all other times. The corresponding banked registers r14_svc, r14_irq, r14_fiq, r14_abt, and r14_und are similarly used to hold the return values of r15 when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines.

Program counter

Register r15 holds the PC. In:

  • ARM state this is word-aligned

  • Thumb state this is halfword-aligned

  • Jazelle state this is byte-aligned.

In privileged modes, another register, the Saved Program Status Register (SPSR), is accessible. This contains the condition code flags and the mode bits saved as a result of the exception that caused entry to the current mode.

Banked registers are discrete physical registers in the core that are mapped to the available registers depending on the current processor operating mode. Banked register contents are preserved across operating mode changes.

Banked registers have a mode identifier that indicates which User mode register they are mapped to. These mode identifiers are shown in Table 2.1.

FIQ mode has seven banked registers mapped to r8–r14 (r8_fiq–r14_fiq). As a result many FIQ handlers do not have to save any registers.

The Supervisor, Abort, IRQ, and Undefined modes each have alternative mode-specific registers mapped to r13 and r14, enabling a private stack pointer and link register for each mode.

Figure 2.3 shows the ARM state registers.

Figure 2.3. Register organization in ARM state

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