2.9.4. Reset

When the nRESET signal is driven LOW a reset occurs, and the processor abandons the executing instruction.

When nRESET is driven HIGH again the processor:

  1. Forces CPSR[4:0] to b10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR T bit and J bit. Other bits in the CPSR are indeterminate.

  2. Forces the PC to fetch the next instruction from the reset vector address.

  3. Reverts to ARM state, and resumes execution.

After reset, all register values except the PC and CPSR are indeterminate.

Refer to Chapter 8 Device Reset for more details of the reset behavior.

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