2.9.5. Fast interrupt request

The Fast Interrupt Request (FIQ) exception supports fast interrupts. In ARM state, FIQ mode has eight banked registers to reduce, or even remove the requirement for storing the previous state of the registers on entry to the interrupt routine (minimizing the overhead of context switching).

An FIQ is externally generated by taking the nFIQ signal input LOW.

Irrespective of whether exception entry is from ARM state, Thumb state, or Jazelle state, an FIQ handler returns from the interrupt by executing:

SUBS PC,R14_fiq,#4

You can disable FIQ exceptions within a privileged mode by setting the CPSR F flag. When the F flag is clear, the processor checks for a LOW level on the nFIQ signal at the end of each instruction.

FIQs and IRQs are disabled automatically when an FIQ occurs. Nested interrupts are allowed but it is up to the programmer to save any corruptible registers and re-enable FIQs and IRQs explicitly.

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