2.9.6. Interrupt request

The IRQ exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ, and is masked on entry to an FIQ sequence. You can disable IRQ at any time, by setting the I bit in the CPSR from a privileged mode.

Irrespective of whether exception entry is from ARM state, Thumb state, or Jazelle state, an IRQ handler returns from the interrupt by executing:

SUBS PC,R14_irq,#4

You can disable IRQ exceptions within a privileged mode by setting the CPSR I flag. When the I flag is clear, the processor checks for a LOW level on the nIRQ signal at the end of each instruction.

IRQs are disabled automatically when an IRQ occurs. Nested interrupts are allowed but it is up to you to save any corruptible registers and to re-enable IRQs.

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