2.9.9. Undefined instruction

When an instruction is encountered that neither the processor, nor any coprocessor in the system can handle, the ARM7EJ-S processor takes the undefined instruction trap. Software can use this mechanism to extend the ARM instruction set by emulating undefined coprocessor instructions.

After emulating the failed instruction, the trap handler must execute the following instruction, irrespective of the processor operating state:

MOVS PC,R14_und

This action restores the CPSR and returns to the next instruction after the undefined instruction.

IRQs are automatically disabled when an undefined instruction trap occurs and are automatically re-enabled on return. For more information about undefined instructions, refer to the ARM Architecture Reference Manual.

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