2.9.11. Exception vectors

You can configure the location of the exception vector addresses using the input CFGHIVECS, as shown in Table 2.4.

Table 2.4. Configuration of exception vector base address locations

Value of CFGHIVECS

Exception vector base location

0

0x0000 0000

1

0xFFFF 0000

Table 2.5 shows the exception vector addresses and entry conditions for the different exception types.

Table 2.5. Exception vectors

Exception

Offset from vector base

Mode on entry

I bit on entry

F bit on entry

Reset

0x00

Supervisor

Disabled

Disabled

Undefined instruction

0x04

Undefined

Disabled

Unchanged

Software interrupt

0x08

Supervisor

Disabled

Unchanged

Abort (prefetch)

0x0C

Abort

Disabled

Unchanged

Abort (data)

0x10

Abort

Disabled

Unchanged

Reserved

0x14

Reserved

-

-

IRQ

0x18

IRQ

Disabled

Unchanged

FIQ

0x1C

FIQ

Disabled

Disabled

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