3.3.1. Nonsequential cycles

A nonsequential cycle is the simplest form of bus cycle, and occurs when the ARM7EJ-S processor requests a transfer to, or from, an address that is unrelated to the address used in the preceding cycle. The memory controller must initiate a memory access to satisfy this request.

The address class signals and TRANS[1:0] is N cycle are broadcast on the bus. At the end of the next bus cycle the data is transferred between the processor and the memory. This is illustrated in Figure 3.2.

Figure 3.2. Nonsequential memory cycle

The processor can perform back-to-back nonsequential memory cycles. This happens, for example, when an STR instruction is executed, as shown in Figure 3.3. If you are designing a memory controller for the processor, and your memory system is unable to cope with this case, you must use the CLKEN signal to extend the bus cycle to allow sufficient cycles for the memory system. For more information, see Using CLKEN to control bus cycles.

Figure 3.3. Back to back memory cycles

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