3.3.2. Sequential cycles

Sequential cycles perform burst transfers on the bus. You can use this information to optimize the design of a memory controller interfacing to a burst memory device, such as a DRAM.

During a sequential cycle, the processor requests a memory location that is part of a sequential burst. If this is the first cycle in the burst, the address can be the same as the previous internal cycle. Otherwise the address is incremented from the previous cycle:

Bursts of byte accesses are not possible.

A burst always starts with an N cycle or a merged I-S cycle (see Figure 3.1), and continues with S cycles. A burst comprises transfers of the same type. The ADDR[31:0] signal increments during the burst. The other address class signals remain the same throughout the burst.

The types of bursts are shown in Table 3.2.

Table 3.2. Burst types

Burst type

Address increment


Word read

4 bytes

Code fetches, or LDM instruction

Word write

4 bytes

STM instruction

Halfword read

2 bytes

Thumb code fetches

All accesses in a burst are of the same width, direction, and protection type. For more details, see Addressing signals.

An example of a burst access is shown in Figure 3.4.

Figure 3.4. Sequential access cycles

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