3.6. Byte and halfword accesses

The ARM7EJ-S processor indicates the size of a transfer using the SIZE[1:0] signals. These are encoded as shown in Table 3.3.

All writable memory in an ARM7EJ-S processor-based system supports the writing of individual bytes to enable the use of the C Compiler and the ARM debug tool chain (for example, Multi-ICE).

The address produced by the ARM7EJ-S processor is always a byte address. However, the memory system ignores the insignificant bits of the address. The significant address bits are shown in Table 3.5.

Table 3.5. Significant address bits

SIZE[1:0]

Width

Significant address bits

b00

Byte

ADDR[31:0]

b01

Halfword

ADDR[31:1]

b10

Word

ADDR[31:2]

When a halfword or byte read is performed, a 32-bit memory system can return the complete 32-bit word, and the ARM7EJ-S processor extracts the valid halfword or byte field from it. The fields extracted depend on the state of the CFGBIGEND signal, which determines the endianness of the system (see Memory formats).

The fields extracted by the ARM7EJ-S processor are shown in Table 3.6.

Table 3.6. Word accesses

SIZE[1:0]

ADDR[1:0]

Little-endian CFGBIGEND=0

Big-endian CFGBIGEND=1

b10

bXX

RDATA[31:0]

RDATA[31:0]

When connecting 8-bit to 16-bit memory systems to the ARM7EJ-S processor, make sure that the data is presented to the correct byte lanes on the processor as shown in Table 3.7 and Table 3.8.

Table 3.7. Halfword accesses

SIZE[1:0]

ADDR[1:0]

Little-endian CFGBIGEND=0

Big-endian CFGBIGEND=1

b01

b0X

RDATA[15:0]

RDATA[31:16]

b01

b1X

RDATA[31:16]

RDATA[15:0]

Table 3.8. Byte accesses

SIZE[1:0]

ADDR[1:0]

Little-endian

Big-endian

b00

b00

RDATA[7:0]

RDATA[31:24]

b00

b01

RDATA[15:8]

RDATA[23:16]

b00

b10

RDATA[23:16]

RDATA[15:8]

b00

b11

RDATA[31:24]

RDATA[7:0]

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