6.5.5. Debug request

A debug request can take place through the EmbeddedICE-RT logic or by asserting the EDBGRQ signal. The request is registered and passed to the processor. Debug request takes priority over any pending interrupt. Following registering, the core enters debug state when:

While waiting for the instruction to finish executing, no more instructions are issued to the Execute stage of the pipeline.

When a hardware debug request occurs, the processor enters debug state even if the EmbeddedICE-RT logic is configured for monitor mode debug.

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