6.5.6. Actions of the processor in debug state

When the processor is in debug state the memory interface indicates internal cycles. This enables the rest of the memory system to ignore the processor and function as normal. Because the rest of the system continues operation, the processor ignores aborts and interrupts.

The CFGBIGEND signal must not be changed by the system while in debug state. If it changes, not only is there a synchronization problem, but the view of the processor seen by the programmer changes without the knowledge of the debugger. The nRESET signal must also be held stable during debug. If the system applies reset to the processor (nRESET is driven LOW), the state of the processor changes without the knowledge of the debugger.

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