9.1.1. Key to tables in this chapter

Table 9.1 shows the key to the other tables in this chapter.

Table 9.1. Key to tables in this chapter

SymbolMeaning
b

The number of busy-wait states during coprocessor accesses.

nThe number of words transferred in any of the following instructions: LDMSTMLDCSTC
C

Coprocessor register transfer cycle (C-cycle).

I

Internal cycle (I-cycle).

N

Nonsequential cycle (N-cycle).

S

Sequential cycle (S-cycle).

pc

The address of the branch instruction.

pc'

The branch target address.

(pc')

The memory contents of the branch target address.

i

4 when in ARM state, or 2 when in Thumb state.

-

Indicates that the signal is not active, and is therefore not valid in this cycle.

 

A blank entry in a table indicates that the status of the signal is not determined by the instruction in that cycle. The status of the signal is determined either by the preceding or following instruction.

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