9.1.2. Instruction cycle counts

Table 9.2 shows the ARM7EJ-S processor instruction cycle counts and bus activity during execution of the ARM instruction set.

Table 9.2. ARM instruction cycle counts and bus activity

InstructionCyclesMemory busComment
CLZ11SAll cases.
Data operation11SNormal case, PC not destination.
Data operation21S+1IWith register controlled shift, PC not destination.
Data operation32S+1NPC destination register, arithmetic data output (ADD, SUB, RSB, ADC, SBC).
Data operation42S+1N+1IPC destination register, logical data output (RSC, ORR, EOR, MOV, BIC).
Data operation42S+1N+1IWith operand shift, PC destination register.
LDR22NNormal case, not loading PC.
LDR22NNot loading PC and following instruction uses loaded word.
LDR31I+2NNot loading PC and shifted offset.
LDR31I+2NNot loading PC and shifted offset and following instruction uses loaded word.
LDR32N+1ILoaded byte, halfword, or unaligned word used by following instruction (1-cycle load-use interlock).
LDR52N+1I+2SPC is destination register.
LDR62N+2I+2SPC is destination register, scaled register offset.
LDRD31S+2NNormal case.
LDRD41S+2NLast loaded word used by following instruction.
STR22NNormal case.
STR31I+2NScaled offset.
STRD31S+2NAll cases.
LDM22NLoading 1 register, not the PC.
LDMn+12N+(n-1)SLoading n registers, n > 1, not loading the PC.
LDMn+12N+(n-1)SLoading n registers, n > 1, not loading the PC, last word loaded used by following instruction.
LDMn+4(n+1)S+2N+1ILoading n registers including the PC, n > 0.
LDM52S+1I+2NLoad PC.
STM22NStoring 1 register.
STMn+1(n-1)S+2NStoring n registers, n > 1.
SWP33NNormal case.
SWP42N+1I+1SSingle-cycle interlock.
B, BL, BX, BLX, BXJ32S+1NAll cases.
SWI, Undefined32S+1NAll cases.
Coprocessor absentb+42S+1N+1I+bIAll cases.
CDPb+21S+(b+1)IAll cases.
LDCb+3(b+1)I+2NLoading 1 register.
STCb+4(b+2)I+1S+1NStoring 1 register.
LDCb+n+2(b+1)I+(n-1)S+2NLoading m registers, m>1.
STCb+n+31N+nS+(b+2)IStoring m registers, m>1.
MCRb+21S+(b+1)IAll cases.
MCRRb+31S+(b+2)IAll cases.
MRCb+21S+(b+1)INormal case.
MRCb+31S+(b+2)IFollowing instruction uses transferred data.
MRRCb+31S+(b+2)INormal case.
MRRCb+41S+(b+3)IFollowing instruction uses last transferred data.
MRS21S+1IAll cases.
MSR11SIf only flags are updated (mask_f).
MSR31S+2IIf any bits other than just the flags are updated (all masks other than mask_f).
MUL, MLA21S+1INormal case.
MUL, MLA 31S+2I Following instruction uses the result in its first Execute cycle or its first Memory cycle. Does not apply to a multiply accumulate using result for accumulate operand.
MULS, MLAS 41S+3IAll cases, sets flags.
QADD, QDADD,QSUB, QDSUB11SNormal case.
QADD, QDADD,QSUB, QDSUB 21S+1IFollowing instruction uses the result in its first Execute cycle.
SMULL, UMULL,SMLAL, UMLAL31S+2INormal case.
SMULL, UMULL,SMLAL, UMLAL41S+3IFollowing instruction uses RdHi result in its first Execute cycle or its first Memory cycle. Does not apply to a multiply accumulate using result for accumulate operand.
SMULLS, UMULLS, SMLALS, UMLALS51S+4IAll cases, sets flags.
SMULxy, SMLAxy11SNormal case.
SMULxy, SMLAxy21S+1IFollowing instruction uses the result in its first Execute or its first Memory cycle. Does not apply to a multiply accumulate using result for accumulate operand.
SMULWx, SMLAWx11SNormal case.
SMULWx, SMLAWx21S+1IFollowing instruction uses the result in its first Execute or its first Memory cycle. Does not apply to a multiply accumulate using result for accumulate operand.
SMLALxy21S+1INormal case.
SMLALxy31S+2IFollowing instruction uses RdHi result in its first Execute cycle or its first Memory cycle. Does not apply to a multiply accumulate using result for accumulate operand.
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