CLZ | 1 | 1S | All cases. |
| Data operation | 1 | 1S | Normal case, PC not destination. |
| Data operation | 2 | 1S+1I | With register controlled shift, PC not destination. |
| Data operation | 3 | 2S+1N | PC destination register, arithmetic data output
(ADD, SUB, RSB, ADC, SBC). |
| Data operation | 4 | 2S+1N+1I | PC destination register, logical data output
(RSC, ORR, EOR, MOV, BIC). |
| Data operation | 4 | 2S+1N+1I | With operand shift, PC destination register. |
LDR | 2 | 2N | Normal case, not loading PC. |
LDR | 2 | 2N | Not loading PC and following instruction uses
loaded word. |
LDR | 3 | 1I+2N | Not loading PC and shifted offset. |
LDR | 3 | 1I+2N | Not loading PC and shifted offset and following instruction
uses loaded word. |
LDR | 3 | 2N+1I | Loaded byte, halfword, or unaligned word used
by following instruction (1-cycle load-use interlock). |
LDR | 5 | 2N+1I+2S | PC is destination register. |
LDR | 6 | 2N+2I+2S | PC is destination register, scaled register
offset. |
LDRD | 3 | 1S+2N | Normal case. |
LDRD | 4 | 1S+2N | Last loaded word used by following instruction. |
STR | 2 | 2N | Normal case. |
STR | 3 | 1I+2N | Scaled offset. |
STRD | 3 | 1S+2N | All cases. |
LDM | 2 | 2N | Loading 1 register, not the PC. |
LDM | n+1 | 2N+(n-1)S | Loading n registers, n > 1, not loading the
PC. |
LDM | n+1 | 2N+(n-1)S | Loading n registers, n > 1, not loading the
PC, last word loaded used by following instruction. |
LDM | n+4 | (n+1)S+2N+1I | Loading n registers including the PC, n > 0. |
LDM | 5 | 2S+1I+2N | Load PC. |
STM | 2 | 2N | Storing 1 register. |
STM | n+1 | (n-1)S+2N | Storing n registers, n > 1. |
SWP | 3 | 3N | Normal case. |
SWP | 4 | 2N+1I+1S | Single-cycle interlock. |
B, BL, BX, BLX, BXJ | 3 | 2S+1N | All cases. |
SWI, Undefined | 3 | 2S+1N | All cases. |
| Coprocessor absent | b+4 | 2S+1N+1I+bI | All cases. |
CDP | b+2 | 1S+(b+1)I | All cases. |
LDC | b+3 | (b+1)I+2N | Loading 1 register. |
STC | b+4 | (b+2)I+1S+1N | Storing 1 register. |
LDC | b+n+2 | (b+1)I+(n-1)S+2N | Loading m registers, m>1. |
STC | b+n+3 | 1N+nS+(b+2)I | Storing m registers, m>1. |
MCR | b+2 | 1S+(b+1)I | All cases. |
MCRR | b+3 | 1S+(b+2)I | All cases. |
MRC | b+2 | 1S+(b+1)I | Normal case. |
MRC | b+3 | 1S+(b+2)I | Following instruction uses transferred data. |
MRRC | b+3 | 1S+(b+2)I | Normal case. |
MRRC | b+4 | 1S+(b+3)I | Following instruction uses last transferred
data. |
MRS | 2 | 1S+1I | All cases. |
MSR | 1 | 1S | If only flags are updated (mask_f). |
MSR | 3 | 1S+2I | If any bits other than just the flags are updated
(all masks other than mask_f). |
MUL, MLA | 2 | 1S+1I | Normal case. |
MUL, MLA | 3 | 1S+2I | Following instruction uses the result in its
first Execute cycle or its first Memory cycle. Does not apply to
a multiply accumulate using result for accumulate operand. |
MULS, MLAS | 4 | 1S+3I | All cases, sets flags. |
QADD, QDADD,QSUB, QDSUB | 1 | 1S | Normal case. |
QADD, QDADD,QSUB, QDSUB | 2 | 1S+1I | Following instruction uses the result in its
first Execute cycle. |
SMULL, UMULL,SMLAL, UMLAL | 3 | 1S+2I | Normal case. |
SMULL, UMULL,SMLAL, UMLAL | 4 | 1S+3I | Following instruction uses RdHi result in its
first Execute cycle or its first Memory cycle. Does not apply to
a multiply accumulate using result for accumulate operand. |
SMULLS, UMULLS, SMLALS, UMLALS | 5 | 1S+4I | All cases, sets flags. |
SMULxy, SMLAxy | 1 | 1S | Normal case. |
SMULxy, SMLAxy | 2 | 1S+1I | Following instruction uses the result in its
first Execute or its first Memory cycle. Does not apply to a multiply accumulate
using result for accumulate operand. |
SMULWx, SMLAWx | 1 | 1S | Normal case. |
SMULWx, SMLAWx | 2 | 1S+1I | Following instruction uses the result in its
first Execute or its first Memory cycle. Does not apply to a multiply accumulate
using result for accumulate operand. |
SMLALxy | 2 | 1S+1I | Normal case. |
SMLALxy | 3 | 1S+2I | Following instruction uses RdHi result in its
first Execute cycle or its first Memory cycle. Does not apply to
a multiply accumulate using result for accumulate operand. |
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