9.10.1. Interlocks

The instructions in this class use both the Execute and Memory stages of the pipeline. For this reason, the result of an instruction in this class is not available until the end of the Memory stage of the pipeline. If a following instruction requires the use of the result, then it must be interlocked so that the correct value is available. This applies to all instructions that require the result for the first Execute cycle. Instructions that require the result of a QADD or similar instruction for the first Memory cycle do not incur an interlock.

As an example, the following sequence incurs a single-cycle interlock:

QADD r0, r1, r2SUB r4, r0, r3

The following cycle does not incur a single-cycle interlock:

QDSUB r0, r1, r2STR r0, [r8]

The following example does not incur an interlock:

QADD r0, r4, r5MLA r0, r3, r4, r0

Table 9.16 shows the cycle timings for QADD, QDADD, QSUB, and QDSUB instructions with and without interlocks.

Table 9.16. Cycle timings for QADD, QDADD, QSUB, and QDSUB

CycleADDRRDATATRANS
Normal1pc+3i(pc+2i)S cycle
   (pc+3i)b
Interlock1pc+3i(pc+2i)I cycle
 2pc+3i-S cycle
   (pc+3i) 
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