9.17.1. Interlocks

A swap operation can cause single-cycle interlocks in a similar way to a load register instruction.

Table 9.24 shows the cycle timing for the basic data swap operation.

Table 9.24. Cycle timings for a basic data swap operation

CycleADDRRDATATRANSLOCKWDATA
Normal1da(pc+2i)N cycle1 
 2da(da)N1 
 3pc+3i-N cycle0Rd
   (pc+3i)   
1-cycle interlock1da(pc+2i)N cycle1 
 2da(da)N cycle1-
 3pc+3i-I cycle0Rd
 4pc+3i-S cycle0-
   (pc+3i)  -
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