Glossary

This glossary describes some of the terms used in this manual. Where terms can have several meanings, the meaning presented here is intended.

Abort

A mechanism that indicates to a core that it should halt execution of an attempted illegal memory access. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. An abort is classified as either a prefetch abort, a data abort, or an external abort.

See Also Data abort, External abort, and Prefetch abort.

Abort model

An abort model is the defined behavior of an ARM processor in response to a Data Abort exception. Different abort models behave differently with regard to load and store instructions that specify base register writeback.

ALU

See Arithmetic Logic Unit.

Application Specific Integrated Circuit

An integrated circuit that has been designed to perform a specific application function. It can be custom-built or mass-produced.

Arithmetic Logic Unit

The part of a processor core that performs arithmetic and logic operations.

ARM state

A processor that is executing ARM (32-bit) word-aligned instructions is operating in ARM state.

ASIC

See Application Specific Integrated Circuit.

Banked registers

Those physical registers whose use is defined by the current processor mode. The banked registers are R8 to R14.

Base register

A register specified by a load or store instruction that is used to hold the base value for the instruction’s address calculation.

Big-endian

Byte ordering scheme in which bytes of decreasing significance in a data word are stored at increasing addresses in memory.

See Also Little-endian and Endianness.

Breakpoint

A breakpoint is a mechanism provided by debuggers to identify an instruction at which program execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register contents, memory locations, variable values at fixed points in the program execution to test that the program is operating correctly. Breakpoints are removed after the program is successfully tested.

See Also Watchpoint.

Byte

An 8-bit data item.

Central Processing Unit

The part of a processor that contains the ALU, the registers, and the instruction decode logic and control circuitry. Also commonly known as the processor core.

CISC

See Complex Instruction Set Computer.

Clock gating

Gating a clock signal for a macrocell with a control signal (such as ETMPWRDOWN) and using the modified clock that results to control the operating state of the macrocell.

Cold reset

Also known as power-on reset. Starting the processor by turning power on. Turning power off and then back on again clears memory and many internal settings. Some program failures lock up the processor and require a cold boot to use the system again. In other cases, only a warm reset is required.

See Also Warm reset.

Complex Instruction Set Computer

The traditional architecture of a computer that uses microcode to execute very comprehensive instructions. Instructions can be variable in length and use all addressing modes, requiring complex circuitry to decode them.

See Also Reduced Instruction Set Computer.

Condition field

A 4-bit field in an instruction that is used to specify a condition under which the instruction can execute.

Content addressable memory

Memory that is identified by its contents. Content addressable memory is used in CAM-RAM architecture caches to store the tags for cache entries.

Control bits

The bottom eight bits of a program status register. The control bits change when an exception arises and can be altered by software only when the processor is in a privileged mode.

Coprocessor

A processor that supplements the main processor. It carries out additional functions that the main processor cannot perform. Usually used for floating-point math calculations, signal processing, or memory management.

Core reset

See Warm reset.

CPU

See Central Processing Unit.

Data Abort

An indication from a memory system to a core that it should halt execution of an attempted illegal memory access. A data abort is attempting to access invalid data memory.

See Also Abort, External abort, and Prefetch abort.

Debug state

A condition that allows the monitoring and control of the execution of a processor. It is usually used to find errors in the application program flow.

Debugger

A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.

Digital Signal Processing

A category of techniques that analyze signals from sources such as sound, weather satellites, and earthquake monitors. Signals are converted into digital data and analyzed using various algorithms such as Fast Fourier Transform.

When a signal has been reduced to numbers, its components can be isolated, analyzed, and rearranged more easily than in analog form. DSP is used in many fields including biomedicine, sonar, radar, seismology, speech and music processing, imaging and communications.

Domain

A collection of sections, large pages and small pages of memory, that can have their access permissions switched rapidly by writing to the Domain Access Control Register (CP15 register 3).

Double word

A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated.

DSP

See Digital Signal Processing.

EmbeddedICE-RT

The additional JTAG-based hardware provided by debuggable ARM processors to aid debugging in real-time.

Endianness

Byte ordering. The scheme that determines the order in which successive bytes of a data word are stored in memory.

See Also Little-endian and Big-endian.

Exception vector

One of a number of fixed addresses in low memory, or in high memory if high vectors are configured, that contains the first instruction of the corresponding interrupt service routine.

External abort

An indication from an external memory system to a core that it should halt execution of an attempted illegal memory access. An external abort is caused by the external memory system as a result of attempting to access invalid memory.

See Also Abort, Data abort, and Prefetch abort.

Halfword

A 16-bit data item.

Instruction cycle count

The number of cycles for which an instruction occupies the Execute stage of the pipeline.

Java

Java is a platform independent object oriented programming language developed by Sun Microsystems. Java is designed to support multi-threaded programming.

See Also Jazelle architecture.

Jazelle architecture

The ARM Jazelle architecture extends the Thumb and ARM operating states by adding a Java state (known as Jazelle state) to the processor. Instruction set support for entering and exiting Java applications, real-time interrupt handling, and debug support for mixed Java/ARM applications is present.

The processor has a new mode in which it behaves like a Java virtual machine. When in Jazelle state, the processor fetches and decodes Java byte codes and maintains the Java operand stack. The processor can switch, under operating system control, between Jazelle state and ARM state.

See Also Java.

Joint Test Action Group

The name of the organization that developed standard IEEE 1149.1. This standard defines a boundary-scan architecture used for in-circuit testing of integrated circuit devices. It is commonly known by the initials JTAG.

JTAG

See Joint Test Action Group.

Little-endian

Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory.

See Also Big-endian and Endianness.

Macrocell

A complex logic block with a defined interface and behavior. A typical VLSI system will comprise several macrocells (such as a processor core, an ETM, and a memory block) plus application-specific logic.

Pipeline

A technique that provide simultaneous, or parallel, processing within the processor. It refers to overlapping operations by moving data or instructions into a conceptual pipe with all stages of the pipe processing simultaneously. For example, while one instruction is being executed, the processor is decoding the next instruction. In vector processors, several steps in a floating point operation can be processed simultaneously. The ARM7EJ-S processor uses a five-stage pipeline when in ARM and Thumb states, and uses a six-stage pipeline when in Jazelle state.

Power-on reset

See Cold reset.

Prefetch abort

An indication from a memory system to a core that it should halt execution of an attempted illegal memory access. A prefetch abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction memory.

See Also Data abort, External abort, and Abort.

Processor

A contraction of microprocessor. A processor includes the CPU or core, plus additional components such as memory, and interfaces. These are combined as a single macrocell, that can be fabricated on an integrated circuit.

Q flag

See Sticky overflow flag.

Reduced Instruction Set Computer

A computer architecture that reduces chip complexity by using simpler instructions. RISC compilers have to generate software routines to perform complex instructions that were previously done in hardware by CISC computers. In RISC, the microcode layer and associated overhead is eliminated.

RISC keeps instruction size constant, bans the indirect addressing mode and retains only those instructions that can be overlapped and made to execute in one machine cycle or less. The RISC chip is faster than its CISC counterpart and is designed and built more economically.

See Also Complex Instruction Set Computer.

Region

A partition of instruction or data memory space.

Register

A temporary storage location used to hold binary data until it is ready to be used.

RISC

See Reduced Instruction Set Computer.

SBO

See Should be one.

SBZ

See Should be zero.

SCREG

The currently selected scan chain number in an ARM TAP controller.

Should be one

Should be written as 1 (or all 1s for bit fields) by software. Writing a 0 will produce UNPREDICTABLE results.

Should be zero

Should be written as 0 (or all 0s for bit fields) by software. Writing a 1 will produce UNPREDICTABLE results.

Sticky overflow flag

Also known as Q flag. A flag that, when set to 1, is not affected by overflow during any other arithmetic instructions. The only instruction that can affect or be affected by the sticky overflow flag is MSR and MRS instructions.

Tag bits

The index or key field of a CAM entry.

TAP

See Test access port.

Test Access Port

The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is TRST.

Thumb state

A processor that is executing Thumb (16-bit) half-word aligned instructions is operating in Thumb state.

UNDEFINED

An instruction that generates an undefined instruction exception.

UNPREDICTABLE

For reads, the data returned when reading from this location is unpredictable. It can have any value. For writes, writing to this location causes unpredictable behavior, or an unpredictable change in device configuration. UNPREDICTABLE instructions must not halt or hang the processor, or any part of the system.

Warm reset

Also known as core reset. Initializes the majority of the processor excluding the TAP controller and EmbeddedICE-RT Logic. This type of reset is useful if you are using the debugging features of the processor.

Watchpoint

A watchpoint is a mechanism provided by debuggers to halt program execution when the data contained by a particular memory address is changed. Watchpoints are inserted by the programmer to enable inspection of register contents, memory locations, and variable values when memory is written to test that the program is operating correctly. Watchpoints are removed after the program is successfully tested.

See Also Breakpoint.

Word

A 32-bit data item.

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