ARM7EJ-S Technical Reference Manual

(Rev 1)


Table of Contents

Preface
About this document
Intended audience
Using this manual
Typographical conventions
Timing diagram conventions
Further reading
Feedback
Feedback on the ARM7EJ-S processor
Feedback on the Technical Reference Manual
1. Introduction
1.1. About the ARM7EJ-S processor with Jazelle technology
1.1.1. The instruction pipelines
1.1.2. Memory access
1.1.3. Forwarding, interlocking, and data dependencies
1.2. ARM7EJ-S processor architecture
1.2.1. Instruction compression
1.2.2. The Thumb instruction set
1.3. ARM7EJ-S processor block, core, and interface diagrams
1.4. ARM7EJ-S processor instruction set summary
1.4.1. Format summary
1.4.2. Extended ARM instruction set summary
1.4.3. Thumb instruction set summary
2. Programmer’s Model
2.1. About the programmer’s model
2.2. Processor operating states
2.2.1. Switching state
2.2.2. Interworking ARM and Thumb state
2.3. Memory formats
2.3.1. Little-endian format
2.3.2. Big-endian format
2.4. Instruction length
2.5. Data types
2.6. Operating modes
2.7. Registers
2.7.1. The ARM state register set
2.7.2. The Thumb state register set
2.7.3. Relationships between ARM state and Thumb state registers
2.7.4. Accessing high registers in Thumb state
2.8. The program status registers
2.8.1. The condition code flags
2.8.2. The Q flag
2.8.3. The J bit
2.8.4. The control bits
2.8.5. Reserved bits
2.9. Exceptions
2.9.1. Exception entry and exit summary
2.9.2. Entering an ARM exception
2.9.3. Leaving an ARM exception
2.9.4. Reset
2.9.5. Fast interrupt request
2.9.6. Interrupt request
2.9.7. Aborts
2.9.8. Software interrupt instruction
2.9.9. Undefined instruction
2.9.10. Breakpoint instruction (BKPT)
2.9.11. Exception vectors
2.9.12. Exception priorities
3. Memory Interface
3.1. About the memory interface
3.2. Bus interface signals
3.3. Bus cycle types
3.3.1. Nonsequential cycles
3.3.2. Sequential cycles
3.3.3. Internal cycles
3.3.4. Merged I-S cycles
3.4. Addressing signals
3.4.1. ADDR[31:0]
3.4.2. WRITE
3.4.3. SIZE[1:0]
3.4.4. PROT[1:0]
3.4.5. LOCK
3.5. Data timed signals
3.5.1. RDATA[31:0]
3.5.2. ABORT
3.5.3. WDATA[31:0]
3.6. Byte and halfword accesses
3.6.1. Writes
3.7. Using CLKEN to control bus cycles
4. Interrupts
4.1. About interrupts
4.2. Hardware interface
4.2.1. Generating an interrupt
4.2.2. Synchronization
4.2.3. Re-enabling interrupts after an interrupt exception
4.3. Maximum interrupt latency
4.4. Minimum interrupt latency
5. Coprocessor Interface
5.1. About the coprocessor interface
5.2. Synchronizing the coprocessor pipeline
5.3. Handshake signals CHSD and CHSE
5.4. LDC operation
5.5. STC operation
5.6. MCR operation
5.7. Coprocessor 15 MCR operation
5.8. MRC operation
5.9. MCRR operation
5.10. MRRC operation
5.11. CDP operation
5.12. Privileged instructions
5.13. Busy-waiting and interrupts
5.14. Operating states
5.15. Connecting coprocessors
5.15.1. Connecting a single coprocessor
5.15.2. Connecting multiple coprocessors
5.16. No external coprocessors
5.17. Undefined instructions
6. Debug Interface and EmbeddedICE-RT
6.1. About the debug interface
6.1.1. Halt mode
6.1.2. Monitor mode
6.2. Debug systems
6.2.1. The debug host
6.2.2. The protocol converter
6.2.3. The ARM7EJ-S processor
6.3. About EmbeddedICE-RT
6.4. Disabling EmbeddedICE-RT
6.5. Debug interface signals
6.5.1. Entry into debug state on breakpoint
6.5.2. Breakpoints and exceptions
6.5.3. Watchpoints
6.5.4. Watchpoints and exceptions
6.5.5. Debug request
6.5.6. Actions of the processor in debug state
6.6. Core clock domains
6.6.1. Clocks and synchronization
6.7. Determining the core and system state
6.8. Debug Communications Channel
6.8.1. DCC registers
6.8.2. DCC control register
6.8.3. DCC monitor mode debug status register
6.8.4. Using the debug communications channel
6.8.5. Debug communications channel reset
6.9. Monitor mode debug
6.10. Using Watchpoints and breakpoints in Jazelle state
6.10.1. Watchpoints
6.10.2. Breakpoints
6.10.3. Monitor mode
7. Embedded Trace Macrocell Interface
7.1. About the ETM interface
7.2. Enabling and disabling the ETM interface
8. Device Reset
8.1. About device reset
8.2. Reset modes
8.2.1. Full system reset
8.2.2. Core reset
8.2.3. EmbeddedICE-RT reset
8.2.4. Normal operation
9. Instruction Cycle Times
9.1. About instruction cycle timings
9.1.1. Key to tables in this chapter
9.1.2. Instruction cycle counts
9.2. Branch and ARM branch with link
9.3. Thumb branch with link
9.4. Branch and Exchange
9.5. Thumb Branch, Link, and Exchange immediate
9.6. Data operations
9.7. MRS
9.8. MSR
9.9. Multiply and multiply accumulate
9.9.1. Interlocks
9.10. QADD, QDADD, QSUB, and QDSUB
9.10.1. Interlocks
9.11. Load register
9.11.1. Interlocks
9.12. Store register
9.13. Load multiple registers
9.14. Store multiple registers
9.15. Load double register
9.16. Store double register
9.17. Data swap
9.17.1. Interlocks
9.18. Software interrupt, undefined instruction, and exception entry
9.19. Coprocessor data processing operation
9.20. Load coprocessor register (from memory)
9.21. Store coprocessor register (to memory)
9.22. Coprocessor register transfer (to ARM)
9.23. Coprocessor register transfer (from ARM)
9.24. Double coprocessor register transfer (to ARM)
9.25. Double coprocessor register transfer (from ARM)
9.26. Coprocessor absent
9.27. Unexecuted instructions
10. AC Parameters
10.1. About the AC parameters
10.2. Memory interface
10.3. Coprocessor interface
10.4. Exception and configuration
10.5. Debug interface
10.6. Interrupt sensitivity
10.7. JTAG interface
10.8. Boundary scan and debug logic output data
10.9. ETM interface
10.10. AC timing parameter definitions
A. Signal Descriptions
A.1. Clock interface signals
A.2. Memory interface signals
A.3. Interrupt signals
A.4. Miscellaneous signals
A.5. Coprocessor interface signals
A.6. Debug signals
A.7. ETM interface signals
B. Debug in Depth
B.1. Scan chains and JTAG interface
B.1.1. Debug scan chains
B.1.2. TAP state machine
B.2. Resetting the TAP controller
B.3. Instruction register
B.4. Public instructions
B.4.1. EXTEST (b0000)
B.4.2. SAMPLE/PRELOAD (b0011)
B.4.3. SCAN_N (b0010)
B.4.4. INTEST (b1100)
B.4.5. IDCODE (b1110)
B.4.6. BYPASS (b1111)
B.4.7. RESTART (b0100)
B.5. Test data registers
B.5.1. Bypass register
B.5.2. Device IDentification (ID) code register
B.5.3. Instruction register
B.5.4. Scan path select register
B.5.5. Scan chains 1 and 2
B.6. Determining the core and system state
B.6.1. Determining the core state
B.6.2. Determining the system state
B.6.3. Exit from debug state
B.7. Behavior of the program counter during debug
B.7.1. ARM and Thumb state breakpoints
B.7.2. ARM and Thumb state watchpoints
B.7.3. Jazelle state breakpoints and watchpoints
B.7.4. Watchpoint with another exception
B.7.5. Watchpoint and breakpoint
B.7.6. Debug request
B.7.7. System speed access
B.7.8. Summary of return address calculations
B.8. Priorities and exceptions
B.8.1. Breakpoint with Prefetch Abort
B.8.2. Interrupts
B.8.3. Data Aborts
B.9. EmbeddedICE-RT logic
B.9.1. Register map
B.9.2. Programming and reading EmbeddedICE-RT logic registers
B.9.3. Using the mask registers
B.9.4. Watchpoint control registers
B.9.5. Debug control register
B.9.6. Debug status register
B.9.7. Vector catch register
B.10. Vector catching
B.11. Coupling breakpoints and watchpoints
B.11.1. Breakpoint and watchpoint coupling example
B.11.2. DBGRNG signal
B.12. Disabling EmbeddedICE-RT
B.13. EmbeddedICE-RT timing
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Five-stage pipeline
1.2. Six-stage Jazelle pipeline
1.3. Block diagram
1.4. Core block diagram
1.5. Interface diagram
2.1. Little-endian addresses of bytes and halfwords within words
2.2. Big-endian addresses of bytes and halfwords within words
2.3. Register organization in ARM state
2.4. Register organization in Thumb state
2.5. Relationships between the ARM state and Thumb state registers
2.6. Program status register
3.1. Simple memory cycle
3.2. Nonsequential memory cycle
3.3. Back to back memory cycles
3.4. Sequential access cycles
3.5. Merged I-S cycle
3.6. Data replication
3.7. Use of CLKEN
4.1. Retaking the FIQ exception
5.1. LDC cycle timing
5.2. STC cycle timing
5.3. MCR cycle timing
5.4. Coprocessor 15 MCR cycle timing
5.5. MRC cycle timing
5.6. MCRR cycle timing
5.7. MRRC cycle timing
5.8. CDP cycle timing
6.1. Typical debug system
6.2. Debug block diagram
6.3. Major debug components
6.4. Breakpoint timing
6.5. Clock synchronization
6.6. DCC control register
6.7. Monitor mode debug status register
8.1. System reset
10.1. Memory interface timing
10.2. Coprocessor interface timing
10.3. Exception and configuration timing
10.4. Debug interface timing
10.5. Interrupt sensitivity timing
10.6. JTAG interface timing
10.7. DBGSDOUT to DBGTDO relationship
10.8. ETM interface timing
B.1. Debug block diagram
B.2. Test access port controller state transitions
B.3. ID code register format
B.4. Typical scan chain cell
B.5. Debug exit sequence
B.6. EmbeddedICE macrocell overview
B.7. Watchpoint control value and mask register format
B.8. Debug control register format
B.9. Debug status register
B.10. Debug control and status register structure
B.11. Vector catch register

List of Tables

1.1. Key to instruction set tables
1.2. ARM instruction set summary
1.3. Addressing modes
1.4. Operand2
1.5. Fields
1.6. Condition fields
1.7. Thumb instruction set summary
2.1. Register mode identifiers
2.2. PSR mode bit values
2.3. Exception entry and exit
2.4. Configuration of exception vector base address locations
2.5. Exception vectors
3.1. Cycle types
3.2. Burst types
3.3. Transfer widths
3.4. PROT[1:0] encoding
3.5. Significant address bits
3.6. Word accesses
3.7. Halfword accesses
3.8. Byte accesses
5.1. Handshake signals
5.2. Coprocessor input signal connections
6.1. Coprocessor 14 register map
8.1. Reset modes
9.1. Key to tables in this chapter
9.2. ARM instruction cycle counts and bus activity
9.3. Cycle timings for branch and ARM branch with link
9.4. Cycle timings for Thumb branch with link
9.5. Cycle timings for Branch and Exchange
9.6. Cycle timings for Thumb Branch, Link, and Exchange
9.7. Cycle timings for data operations
9.8. Cycle timings for MRS
9.9. Cycle timings for MSR
9.10. Cycle timing for MUL and MLA
9.11. Cycle timings for MULS and MLAS
9.12. Cycle timing for SMULL, UMULL, SMLAL, and UMLAL
9.13. Cycle timings for SMULLS, UMULLS, SMLALS, and UMLALS
9.14. Cycle timings for SMULxy, SMLAxy, SMULWy, and SMLAWy
9.15. Cycle timings for SMLALxy
9.16. Cycle timings for QADD, QDADD, QSUB, and QDSUB
9.17. Cycle timings for basic load register operations
9.18. Cycle timings for load operations resulting in simple interlocks
9.19. Cycle timings for an example LDRB, ADD and ADD sequence
9.20. Cycle timings for an example LDRB and STMIA sequence
9.21. Cycle timings for a store register operation
9.22. Cycle timings for LDM
9.23. Cycle timings for STM
9.24. Cycle timings for a basic data swap operation
9.25. Exception entry cycle timings
9.26. Cycle timings for coprocessor data operations
9.27. Cycle timings for load coprocessor register operations
9.28. Cycle timings for STC
9.29. Cycle timings for MRC
9.30. Cycle timings for MCR
9.31. Cycle timings for MRRC
9.32. Cycle timings for MCRR
9.33. Cycle timings for coprocessor absent
9.34. Cycle timing for unexecuted instructions
10.1. Memory interface timing parameters
10.2. Coprocessor interface timing parameters
10.3. Exception and configuration timing parameters
10.4. Debug interface timing parameters
10.5. Interrupt sensitivity timing parameters
10.6. JTAG interface timing parameters
10.7. DBGSDOUT to DBGTDO relationship timing parameters
10.8. ETM interface timing parameters
10.9. Target AC timing parameters
A.1. Clock interface signals
A.2. Memory interface signals
A.3. Interrupt signals
A.4. Miscellaneous signals
A.5. Coprocessor interface signals
A.6. Debug signals
A.7. ETM interface signals
B.1. Public instructions
B.2. Scan chain number allocation
B.3. Scan chain 1 bit order
B.4. EmbeddedICE-RT logic register map
B.5. SIZE bits
B.6. Debug control register bit functions
B.7. Interrupt signal control
B.8. Debug status register bit functions
B.9. Method of entry

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This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Figure B.2 reprinted with permission IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture Copyright 2001, by IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A1 May 2001Internal release
Revision B18 December 2001Release for Rev 1
Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B
Non-Confidential