Using this manual

This document is organized into the following chapters:

Chapter 1 Introduction

Read this chapter for an introduction to the ARM7EJ-S processor and a summary of the instruction set.

Chapter 2 Programmer’s Model

Read this chapter for a description of the ARM7EJ-S processor from the point of view of the programmer.

Chapter 4 Interrupts

Read this chapter for a description of interrupt operation, including interrupt latency.

Chapter 3 Memory Interface

Read this chapter for a description of the memory signals, including descriptions of the sequential, nonsequential, internal, and coprocessor register transfer bus cycles.

Chapter 5 Coprocessor Interface

Read this chapter for a description of the coprocessor interface, including timing diagrams for coprocessor operations.

Chapter 6 Debug Interface and EmbeddedICE-RT

Read this chapter for a description of the debug interface and the EmbeddedICE-RT Logic.

Chapter 7 Embedded Trace Macrocell Interface

Read this chapter for a description of the Embedded Trace Macrocell interface and signals.

Chapter 8 Device Reset

Read this chapter for a description of the reset behavior of the ARM7EJ-S processor.

Chapter 9 Instruction Cycle Times

Read this chapter for a summary of instruction cycle timings and a description of interlocks.

Chapter 10 AC Parameters

Read this chapter for the main AC timing parameters of the ARM7EJ-S processor.

Appendix A Signal Descriptions

Read this chapter for a description of all the ARM7EJ-S processor interface signals.

Appendix B Debug in Depth

Read this chapter for a detailed description of the debug interface and additional information about the EmbeddedICE-RT logic.

Copyright ©  2001 ARM Limited. All rights reserved.ARM DDI 0214B
Non-Confidential