PrimeCell™ MultiPort Memory Controller (PL172) Technical Reference Manual 2.1. MPMC functional description

2.1. MPMC functional description

Figure 2.1 shows a block diagram of the MPMC.

Figure 2.1. MPMC block diagram

Note

In Figure 2.1 the letter x in the AHB slave memory interface signals denotes a number between 0-3.

The MPMC block optimizes and controls external memory transactions.

The following sections describe the functions of the MPMC blocks:

AHB slave register interface
AHB slave memory interfaces
Data buffers
Arbiter
Memory controller state machine
Pad interface
Test Interface Controller (TIC).

Note

For 32-bit wide chip selects data is transferred to and from dynamic memory in SDRAM bursts of four. For 16-bit wide chip selects SDRAM bursts of eight are used.

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