PrimeCell™ MultiPort Memory Controller (PL172) Technical Reference Manual 3.3.23. Static Memory Output Enable Delay Registers 0-3

3.3.23. Static Memory Output Enable Delay Registers 0-3

The four-bit, read/write, MPMCStaticWaitOen0-3 Registers enable you to program the delay from the chip select or address change, whichever is later, to the output enable. It is recommended that you modify this register during system initialization, or when there are no current or outstanding transactions. You can ensure this by waiting until the MPMC is idle, and then entering low-power, or disabled mode. These registers are accessed with one wait state.

Figure 3.23 shows the register bit assignments.

Figure 3.23. MPMCStaticWaitOen0-3 Registers bit assignments

Table 3.26 lists the register bit assignments.

Table 3.26. MPMCStaticWaitOen0-3 Registers bit assignments

Bits	Name	Function
[31:4]	-	Read undefined. Write as zero.
[3:0]	Wait output enable, WAITOEN	Delay from chip select assertion to output enable. 0000 = No delay (reset value on nPOR) 0001-1111= n cycle delay^[1].
^[1]The delay is WAITOEN x t_HCLK.

Bits

Name

Function

[31:4]

Read undefined. Write as zero.

[3:0]

Wait output enable, WAITOEN

Delay from chip select assertion to output enable.

0000 = No delay (reset value on nPOR)

0001-1111= n cycle delay^[1].

^[1]The delay is WAITOEN x t_HCLK.

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