PrimeCell ™ MultiPortMemory Controller (PL172) Technical Reference Manual


Table of Contents

About this manual
Product revision status
Intended audience
Using this manual
Further reading
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the PrimeCell MultiPort MemoryController (PL172)
1.1.1. Features
1.2. Supported dynamic memory devices
1.2.1. Examples of JEDEC SDRAM devices
1.2.2. Examples of Micron synchronous flashtype devices
1.2.3. Examples of JEDEC low-power SDRAMdevices
1.3. Supported static memory devices
1.3.1. Examples of ROM devices
1.3.2. Examples of page mode ROM devices
1.3.3. Examples of SRAM devices
1.3.4. Examples of flash devices
1.3.5. Examples of page mode flash devices
1.4. Product revisions
1.4.1. r1p0-r2p2
1.4.2. r2p2-r2p3
1.4.3. r2p3-r2p4
2. Functional Overview
2.1. MPMC functional description
2.1.1. AHB slave register interface
2.1.2. AHB slave memory interfaces
2.1.3. Data buffers
2.1.4. Arbiter
2.1.5. Memory controller state machine
2.1.6. Pad interface
2.1.7. Test Interface Controller (TIC)
2.2. Overview of an example MPMC system
2.2.1. External bus
2.2.2. Internal bus
2.3. Low-power operation
2.3.1. Low-power SDRAM deep-sleep mode
2.3.2. Low-power SDRAM partial array refresh
2.4. Locked accesses
2.5. Burst types
2.6. Busy transfer type
2.7. Arbitration
2.7.1. Re-arbitration occurrence
2.7.2. Re-arbitration priority
2.8. Worst-case transaction latency
2.8.1. Worst-case transaction latency forthe highest priority AHB memory port
2.8.2. System factors effecting worst-caselatency
2.9. Memory bank select
2.10. Memory map
2.10.1. Power-on reset memory map
2.10.2. Chip select 1 memory configuration
2.10.3. Boot from flash, SRAM remapped after boot
2.10.4. Example of a boot from flash, SDRAM remapped afterboot
2.10.5. Memory aliasing
2.10.6. AHB port address map
2.10.7. Unused AHB HADDRx address bits
2.11. Sharing memory interface signals
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Summary of registers
3.3. Register descriptions
3.3.1. Control Register
3.3.2. Status Register
3.3.3. Configuration Register
3.3.4. Dynamic Memory Control Register
3.3.5. Dynamic Memory Refresh Timer Register
3.3.6. Dynamic Memory Read ConfigurationRegister
3.3.7. Dynamic Memory Precharge Command PeriodRegister
3.3.8. Dynamic Memory Active To PrechargeCommand Period Register
3.3.9. Dynamic Memory Self-refresh Exit TimeRegister
3.3.10. Dynamic Memory Last Data Out To ActiveTime Register
3.3.11. Dynamic Memory Data-in To Active CommandTime Register
3.3.12. Dynamic Memory Write Recovery TimeRegister
3.3.13. Dynamic Memory Active To Active CommandPeriod Register
3.3.14. Dynamic Memory Auto-refresh PeriodRegister
3.3.15. Dynamic Memory Exit Self-refresh Register
3.3.16. Dynamic Memory Active Bank A to ActiveBank B Time Register
3.3.17. Dynamic Memory Load Mode RegisterTo Active Command Time Register
3.3.18. Static Memory Extended Wait Register
3.3.19. Dynamic Memory Configuration Registers0-3
3.3.20. Dynamic Memory RAS and CAS Delay Registers0-3
3.3.21. Static Memory Configuration Registers0-3
3.3.22. Static Memory Write Enable Delay Registers0-3
3.3.23. Static Memory Output Enable DelayRegisters 0-3
3.3.24. Static Memory Read Delay Registers0-3
3.3.25. Static Memory Page Mode Read DelayRegisters 0-3
3.3.26. Static Memory Write Delay Registers0-3
3.3.27. Static Memory Turn Round Delay Registers0-3
3.3.28. Conceptual Additional Peripheral IdentificationRegisters
3.3.29. Peripheral Identification Registers
3.3.30. PrimeCell Identification Registers 0-3
4. Programmer’s Model for Test
4.1. MPMC test harness overview
4.1.1. AMBA test strategy
4.1.2. Non-AMBA intra-chip integration test strategy
4.1.3. Primary I/O test strategy
4.2. Production test
4.3. Summary of test registers
4.4. Test register descriptions
4.4.1. Test Control Register
4.4.2. Test Input Register
4.4.3. Test Output Register
A. Signal Descriptions
A.1. AHB register signals
A.2. AHB memory signals
A.3. Miscellaneous signals
A.3.1. Tie-off signals
A.3.2. Test signals
A.3.3. Clock signals
A.3.4. External Bus Interface (EBI) signals
A.4. Pad interface and control signals
A.5. Test Interface Controller (TIC) AHBsignals
A.6. Scan test signals

List of Figures

2.1. MPMC block diagram
2.2. Pad interface block diagram
2.3. TIC block diagram
2.4. MPMC in an example system
3.1. MPMCControl Register bit assignments
3.2. MPMCStatus Register bit assignments
3.3. MPMCConfig Register bit assignments
3.4. MPMCDynamicControl Register bit assignments
3.5. MPMCDynamicRefresh Register bit assignments
3.6. MPMCDynamicReadConfig Register bitassignments
3.7. MPMCDynamictRP Register bit assignments
3.8. MPMCDynamictRAS Register bit assignments
3.9. MPMCDynamictSREX Register bit assignments
3.10. MPMCDynamictAPR Register bit assignments
3.11. MPMCDynamictDAL Register bit assignments
3.12. MPMCDynamictWR Register bit assignments
3.13. MPMCDynamictRC Register bit assignments
3.14. MPMCDynamictRFC Register bit assignments
3.15. MPMCDynamictXSR Register bit assignments
3.16. MPMCDynamictRRD Register bit assignments
3.17. MPMCDynamictMRD Register bit assignments
3.18. MPMCStaticExtendedWait Register bitassignments
3.19. MPMCDynamicConfig0-3 Registers bitassignments
3.20. MPMCDynamicRasCas0-3 Registers bitassignments
3.21. MPMCStaticConfig0-3 Registers bitassignments
3.22. MPMCStaticWaitWen0-3 Registers bitassignments
3.23. MPMCStaticWaitOen0-3 Registers bitassignments
3.24. MPMCStaticWaitRd0-3 Registers bitassignments
3.25. MPMCStaticWaitPage0-3 Registers bitassignments
3.26. MPMCStaticWaitWr0-3 Registers bitassignments
3.27. MPMCStaticWaitTurn0-3 Registers bitassignments
3.28. Conceptual MPMC Additional PeripheralID Register bit assignments
3.29. Peripheral Identification Registerbit assignment
3.30. Conceptual PrimeCell ID Registerbit assignments
4.1. MPMCITCR Register bit assignments
4.2. MPMCITIP Register bit assignments
4.3. MPMCITOP Register bit assignments

List of Tables

2.1. Memory bank selection
3.1. MPMC register summary
3.2. MPMCControl Register bit assignments
3.3. MPMCStatus Register bit assignments
3.4. MPMCConfig Register bit assignments
3.5. MPMCDynamicControl Register bit assignments
3.6. Output voltage settings
3.7. MPMCDynamicRefresh Register bit assignments
3.8. MPMCDynamicReadConfig Register bit assignments
3.9. MPMCDynamictRP Register bit assignments
3.10. MPMCDynamictRAS Register bit assignments
3.11. MPMCDynamictSREX Register bit assignments
3.12. MPMCDynamictAPR Register bit assignments
3.13. MPMCDynamictDAL Register bit assignments
3.14. MPMCDynamictWR Register bit assignments
3.15. MPMCDynamictRC Register bit assignments
3.16. MPMCDynamictRFC Register bit assignments
3.17. MPMCDynamictXSR Register bit assignments
3.18. MPMCDynamictRRD Register bit assignments
3.19. MPMCDynamictMRD Register bit assignments
3.20. MPMCStaticExtendedWait Register bit assignments
3.21. MPMCDynamicConfig0-3 Registers bit assignments
3.22. Address mapping
3.23. MPMCDynamicRasCas0-3 Registers bit assignments
3.24. MPMCStaticConfig0-3 Registers bit assignments
3.25. MPMCStaticWaitWen0-3 Registers bit assignments
3.26. MPMCStaticWaitOen0-3 Registers bit assignments
3.27. MPMCStaticWaitRd0-3 Registers bit assignments
3.28. MPMCStaticWaitPage0-3 Registers bit assignments
3.29. MPMCStaticWaitWr0-3 Registers bit assignments
3.30. MPMCStaticWaitTurn0-3 Registers bit assignments
3.31. Conceptual MPMC Additional Peripheral ID Register bit assignments
3.32. MPMCPeriphID4 Register bit assignments
3.33. MPMCPeriphID5-7 Registers bit assignments
3.34. Conceptual MPMC Peripheral ID Register bit assignments
3.35. MPMCPeriphID0 Register bit assignments
3.36. MPMCPeriphID1 Register bit assignments
3.37. MPMCPeriphID2 Register bit assignments
3.38. MPMCPeriphID3 Register bit assignments
3.39. Conceptual PrimeCell ID Register bit assignments
4.1. Test registers memory map
4.2. MPMCITCR Register bit assignments
4.3. MPMCITIP Register bit assignments
4.4. MPMCITOP Register bit assignments
A.1. AHB register signal descriptions
A.2. AHB memory signal descriptions
A.3. Miscellaneous and clock signal descriptions
A.4. Test signal descriptions
A.5. Clock signal descriptions
A.6. EBI signal descriptions
A.7. Pad interface and control signal descriptions
A.8. TIC AHB signal descriptions
A.9. Scan test signal descriptions

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.


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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A January2002 First release.
Revision B July2002 Second release.
Revision C March2003 Third release for r2p2.
Revision D 22March 2004 Fourth release for r2p3.The descriptionof the HCLK:MPMCCLKOUT ratio, set in the MPMCConfig Register isclarified. See Configuration Register on page 3-10.
Revision E 27 April2006 Fifth release for r2p4.The description ofthe size of the row address synchronous memory parts that the controllersupports is corrected. See Features on page 1-2.The descriptionof the MPMCDQMOUT[3:0] signal is corrected. See Pad interface andcontrol signals on page A-11.
Copyright © 2002-2006 ARM Limited. All rights reserved. ARM DDI 0215E