HADDRM[31:0]

Output

AHB slave

32-bit system address bus.

HBURSTM[2:0]

Output

AHB slave

Indicates whether the transfer is a burst transfer.

HLOCKDMACM

Output

AHB slave

This signal indicates to the arbiter that the requesting master is going to perform a number of indivisible transfers. It also indicates that the arbiter must not grant the bus to another bus master when the first of the locked transfers has commenced.

HPROTM[3:0]

Output

AHB slave

Protection control. Provides information about a bus access.

HRDATAM[31:0]

Input

AHB slave

The read data bus transfers data from bus slaves to the bus master during read operations.

HREADYINM

Input

AHB slave

When HIGH, the HREADY signal indicates that a transfer has finished on the bus. You can drive this signal LOW to extend a transfer.

HRESPM[1:0]

Input

AHB slave

The transfer response provides additional information on the status of a transfer. Four different responses are provided

The slave uses the OKAY response to indicate that the transfer has completed successfully.

The slave uses the ERROR response to indicate that an error has occurred. The SMDMAC then asserts the Error Interrupt request.

The slave uses the RETRY and SPLIT responses to indicate that the data is not ready. The SMDMAC must retry the transfer later.

HSIZEM[2:0]

Output

AHB slave

Indicates the size of the transfer. This is typically:

The SMDMAC enables 8, 16, and 32-bit transfer widths:

8-bit: HSIZE[2:0] = 0b000

16-bit: HSIZE[2:0] = 0b001

32-bit: HSIZE[2:0] = 0b010.

HTRANSM[1:0]

Output

AHB slave

Indicates the type of the current transfer. This can be:

HWDATAM[31:0]

Output

AHB slave

The write data bus transfers data from the master to the bus slaves during write operations.

HWRITEM

Output

AHB slave

When HIGH, this signal indicates a write transfer, and when LOW, a read transfer.