PrimeCell® Single Master DMA Controller (PL081) Technical Reference Manual 3.4.14. Synchronization Register

3.4.14. Synchronization Register

The DMACSync Register, with address offset of 0x034, is read/write and enables or disables synchronization logic for the DMA request signals. The DMA request signals consist of the DMACBREQ[15:0], DMACSREQ[15:0], DMACLBREQ[15:0], and DMACLSREQ[15:0]. A bit set to 0 enables the synchronization logic for a particular group of DMA requests. A bit set to 1 disables the synchronization logic for a particular group of DMA requests. This register is reset to 0, synchronization logic enabled.

Note

You must use synchronization logic when the peripheral generating the DMA request runs on a different clock to the SMDMAC. For peripherals running on the same clock as the SMDMAC, disabling the synchronization logic improves the DMA request response time. If necessary, you must synchronize the DMA response signals, DMACCLR and DMACTC, in the peripheral.

Figure 3.14 shows the register bit assignments.

Figure 3.14. DMACSync Register bit assignments

Table 3.15 lists the register bit assignments.

Table 3.15. DMACSync Register bit assignments

Bit	Name	Function
[31:16]	-	Read undefined.
[15:0]	DMACSync	DMA synchronization logic for DMA request signals enabled or disabled. A LOW bit indicates that the synchronization logic for the DMACBREQ[15:0], DMACSREQ[15:0], DMACLBREQ[15:0], and DMACLSREQ[15:0] request signals is enabled. A HIGH bit indicates that the synchronization logic is disabled.

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